Electrothermal Frequency References in Standard CMOS by S. Mahdi Kashmiri & Kofi A. A. Makinwa

Author:S. Mahdi Kashmiri & Kofi A. A. Makinwa
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

4.2.2 DAFLL System-Level Specifications

In order to derive a set of system-level specifications for the proposed DAFLL, the more detailed block-diagram shown in Fig. 4.3 is considered. The square-wave output of the DCO, f DCO , enters a frequency divider. This produces the sampling clock, f s , and the ETF drive signal, f drive , which are both sub-multiples of f DCO . The ETF output is then applied to the PDΔΣM, which digitizes the ETF phase shift with reference to two phase references, f drive (φ 0) or f drive (φ 1), produced by the divider. These are also square-wave signals, which are ±45° phase-shifted regarding to f drive [7, 8]. The bitstream output of the modulator is then a digital representation of the ETF’s phase shift.

Fig. 4.3Detailed block-diagram of the digitally-assisted electrothermal FLL

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